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16 - channel das with 16 - bit, bipolar input, dual simultaneous sampling adc data sheet ad7616 - p rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or paten t rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2017 analog devices, inc. all rights reserved. technical support www.analog.com features 16 - channel , dual , simultaneously sampled inputs independently selectable channel input ranges true bipolar: 10 v, 5 v , 2.5 v single 5 v analog supply and 2.3 v to 3.6 v v drive supply fully integrated data acquisition s olution analog input clamp protection input buffer with 1 m analog input impedance 1st - order antialiasing analog filter on - chip accurate reference and reference buffer dual 16 - bit sar adc throughput rate: 2 1 m sps oversampling capability with digital filter flexible sequencer with burst mode parallel digital interface optional crc error checking hardware/ s oftware configuration performance 92 db snr at 500 k sps (2 osr ) 90.5 db snr at 1 m sps ? 103 db thd 1 lsb inl (typical) , 0.99 lsb dnl (maximum) 8 kv esd rating on analog input pins on - chip self detect function 80 - lead lqfp package applications power line monitoring protective r elays multiphase motor control instrumentation and control systems data acquisition systems (das s ) general d escription the ad7616 - p is a 16 - bit, das that supports dual simultaneous sampling of 16 channels. the ad7616 - p operates from a single 5 v supply and can accommodate 10 v, 5 v , and 2.5 v true bipolar input signals whil e sampling at throughput rates up to 1 m sps per channe l pair with 90 .5 db snr. higher signal - to - noise ratio (snr) performance can be achieved wit h the on - chip oversampling mode ( 92 db for an oversampling ratio (osr) of 2 ) . the input clamp protection circuitry tolerate s voltages up to 2 1 v. t h e ad7616 - p has 1 m? analog input impedance , regardless of sampling frequency. the single - supply operation, on - chip filtering, and high input impedance eliminate the need for driver op amps and external bipolar su pplies. the device contains analog input clamp protection, a dual , 16 - bit charge redistribution successive approximation register (sar) analog - to - digital converter (adc), a flexible digital filter, a 2.5 v reference and reference buffer, and a high speed p arallel interface . functional block dia gram figure 1. first- order lpf first- order lpf 9:1 mux busy convst control inputs clk osc refinout refsel par osr digital filter 2.5v ref refcap v cc agnd regcap regcapd 1.8v dldo 9:1 mux 16-bit sar 16-bit sar v drive 2:1 mux hw_rngsel0, hw_rngsel1 chsel2 to chsel0 seqen flexible sequencer wr/burst reset dgnd db15 to db0 parallel first- order lpf clamp clamp first- order lpf 1.8v aldo parallel interface 1m? r fb r fb 1m? v0a v0agnd v7a v7agnd v0b v0bgnd v7b v7bgnd clamp clamp 1m? r fb r fb 1m? clamp clamp 1m? r fb r fb 1m? clamp clamp 1m? r fb r fb 1m? v cc aldo AD7616-P 15695-001
AD7616-P* product page quick links last content update: 07/07/2017 comparable parts view a parametric search of comparable parts. evaluation kits ? ad7616/AD7616-P evaluation board documentation application notes ? an-1416: setup example for configuring the ad7616 for high dynamic range applications data sheet ? AD7616-P: 16-channel das with 16-bit, bipolar input, dual simultaneous sampling adc data sheet user guides ? ug-1012: evaluating the ad7616/AD7616-P 16-channel das with 16-bit, bipolar input, dual simultaneous sampling adc software and systems requirements ? ad7616 no-os/hdl drivers tools and simulations ? ad7616 ibis model design resources ? AD7616-P material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all AD7616-P engineerzone discussions. sample and buy visit the product page to see pricing options. technical support submit a technical question or find your regional support number. document feedback submit feedback for this data sheet. this page is dynamically generated by analog devices, inc., and inserted into this data sheet. a dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. this dynamic page may be frequently modified.
ad7616- p data sheet rev. 0 | page 2 of 46 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revi sion history ............................................................................... 2 specifications ..................................................................................... 3 timing specifications .................................................................. 6 absolute maximum ratings ............................................................ 9 thermal resistance ...................................................................... 9 esd caution .................................................................................. 9 pin configuration and function descriptions ........................... 10 typical performance characteristics ........................................... 13 terminology .................................................................................... 19 theory of operation ...................................................................... 21 converter details ........................................................................ 21 analog input ............................................................................... 21 adc transfer fun ction ............................................................. 22 internal/external reference ...................................................... 22 shutdown mode .......................................................................... 23 digital filter ................................................................................ 23 applications i nformation .............................................................. 24 functionality overview ............................................................. 24 power supplies ............................................................................ 24 typical connections .................................................................. 24 device c onfiguration ..................................................................... 25 operational mode ...................................................................... 25 internal/external reference ...................................................... 25 hardware mode .......................................................................... 25 software mode ............................................................................ 26 reset functionality ..................................................................... 26 pin function overview ............................................................. 26 digital interface .............................................................................. 27 channel se lection ....................................................................... 27 parallel interface ......................................................................... 28 sequencer ......................................................................................... 30 hardware mode sequencer ....................................................... 30 software mode sequencer ......................................................... 30 burst sequencer .......................................................................... 31 diagnostics ...................................................................................... 33 diagnostic channels .................................................................. 33 interfac e self test ....................................................................... 33 crc .............................................................................................. 33 register summary .......................................................................... 35 addressing registers .................................................................. 36 configuration register .............................................................. 37 channel register ........................................................................ 38 input range registers ................................................................ 39 sequencer stack registers ......................................................... 42 st atus register ............................................................................. 45 outline dimensions ....................................................................... 46 ordering guide .......................................................................... 46 revision history 6 /2017 revision 0 : initial version
data sheet ad7616- p rev. 0 | page 3 of 46 specifications v ref = 2.5 v external/internal, v cc = 4.75 v to 5.25 v, v drive = 2.3 v to 3.6 v, f sample = 1 m sps, t a = ?40c to +125c , unless otherwise noted. table 1 . parameter test conditions/comments min typ max unit dynamic performance f in = 1 khz sine wave , unless otherwise noted snr 1 , 2 no o versampling , 10 v range 89 90.5 db osr = 2 , 10 v range , 3 f sample = 500 ksps 92 db osr = 4 , 10 v range 3 93 db no oversampling , 5 v r ange 88 8 9.5 db no oversampling , 2.5 v range 85.5 8 7 db signal - to - noise - and - distortion (sinad) 1 no oversampling , 10 v range 8 8.5 90 db no oversampling , 5 v range 87.5 89 db no oversampling , 2.5 v range 8 5 87 db dynamic range no oversampling , 10 v range 9 2 db no oversampling , 5 v range 90.5 db no oversampling , 2.5 v range 8 8 db total harmonic distortion (thd) 1 no oversampling, 10 v range ?103 ? 9 2 .5 db no oversampling, 5 v range ?100 db no oversampling, 2.5 v range ? 97 db peak harmonic or spurious noise 1 ? 103 db intermodulation distortion (imd) 1 fa = 1 khz, fb = 1.1 khz second - order terms ?10 5 db third - order terms ? 1 13 db channel to channel isolation 1 f in on unselected channels up to 5 khz ? 106 db analog input filter full power bandwidth ?3 db , 10 v range 39 khz ?3 db, 5 v/2.5 v range 33 khz ?0.1 db 5.5 khz phase delay 1 , 3 10 v range 4. 4 6 s 5 v range 5 s 2.5 v range 4.9 s drift 1 , 3 10 v range 0.55 5 ns/ c matching (d ual simultaneous pair) 3 10 v range 4.4 100 ns 5 v range 4.7 ns 2.5 v range 4.1 ns dc accuracy resolution no missing codes 16 bits differential nonlinearity (dnl) 1 0.5 0.99 lsb 4 integral nonlinearity (inl) 1 1 2 lsb 4 total unadjusted error (tue) 10 v range 6 lsb 4 5 v range 8 lsb 4 2.5 v range 10 lsb 4 positive full - scale (pfs) error 1 , 5 external reference 10 v range 5 3 8 lsb 4 5 v range 4 lsb 4 2.5 v range 2 lsb 4 internal reference 10 v range 5 lsb 4 drift 3 external reference 2 5 ppm/c internal reference 3 10 ppm/c matching 1 10 v range 3 11 lsb 4 5 v range 4 lsb 4
ad7616- p data sheet rev. 0 | page 4 of 46 parameter test conditions/comments min typ max unit 2.5 v range 8 lsb 4 bipolar zero code error 1 10 v range 0.8 8 lsb 4 5 v range 1 10 lsb 4 2.5 v range 3 15 lsb 4 drift 3 10 v range 1.3 20.4 v/c 5 v range 0.9 v/c 2.5 v range 0.5 v/c matching 1 10 v range 2 10 lsb 4 5 v range 3 lsb 4 2.5 v range 3 lsb 4 negative full - scale (nfs) error 1 , 6 external reference 10 v range 4 3 8 lsb 4 5 v range 3 lsb 4 2.5 v range 6 lsb 4 internal reference 10 v range 3 lsb 4 drift 3 external reference 2 5 ppm/c internal reference 4 10 ppm/c matching 1 10 v range 3 1 1 lsb 4 5 v range 4 lsb 4 2.5 v range 8 lsb 4 analog input input voltage ranges software/hardware selectable 10 v software/hardware selectable 5 v software/hardware selectable 2.5 v analog input current 10 v range, see figure 33 10.5 a 5 v range, see figure 33 6.5 a 2.5 v range, see figure 33 4 a input capacitance 6 10 pf input impedance see the analog input section 0.85 1 m input impedance drift 3 25 ppm/c reference input/output reference input voltage range see the adc transfer function section 2.495 2.5 2.505 v dc leakage current 1 a input capacitance 6 refsel = 1 7.5 pf reference output voltage refinout 2.495 2.505 v reference temperature coefficient 3 2 15 ppm/c logic inputs input voltage high (v inh ) v drive = 2.7 v to 3.6 v 2 v v drive = 2.3 v to 2.7 v 1.7 v low (v inl ) v drive = 2.7 v to 3.6 v 0.8 v v drive = 2.3 v to 2.7 v 0.7 v input current (i in ) 1 a input capacitance (c in ) 6 5 pf logic outputs output voltage high (v oh ) i source = 100 a v drive ? 0.2 v low (v ol ) i sink = 100 a 0.4 v floating state leakage current 0.005 1 a floating state output capacitance 6 5 pf output coding twos complement
data sheet ad7616- p rev. 0 | page 5 of 46 parameter test conditions/comments min typ max unit conversion rate per channel pair conversion time 0.5 s acquisition time 0.5 s throughput rate 1 msps power requirements v cc 4.75 5.25 v v drive 2.3 3.6 v v cc pin current, i vcc normal mode static 37 57 ma operational f sample = 1 msps 42 65 ma shutdown mode 28 a i drive digital inputs = 0 v or v drive normal mode static 0.3 0.9 5 ma operational f sample = 1 msps 2.4 3.2 ma shutdown mode 2 0 a power dissipation normal mode static 185 300 mw operational f sample = 1 msps 230 360 mw shutdown mode 0. 2 5 mw 1 see the terminology section. 2 the user can achieve 93 db snr by enabling oversampling. the values are valid for manual mode. in burst mode, values degrade by ~1 db. 3 not production tested. sample tested during initial release to ensure compliance. 4 lsb means least significant bit. with a 2.5 v input range, 1 lsb = 76.293 v. with a 5 v input range, 1 lsb = 152.58 v. wi th a 10 v input range, 1 lsb = 305.175 v. 5 positive and negative full - scale error for the internal reference excludes reference errors. 6 supported by simulation data.
ad7616- p data sheet rev. 0 | page 6 of 46 timing specification s note that throughout the timing specifications, multifunction pins, such as wr / burst, are referred to either by the entire pin name or by a single function of the pin, for example, wr , when only that function is relevant. universal timing specifications v cc = 4.75 v to 5.25 v, v drive = 2.3 v to 3.6 v, v ref = 2.5 v external reference/internal reference, t a = ? 40 c to + 125c , unless otherwise noted. interface timing tested using a load capacitance of 30 pf . table 2 . parameter 1 min typ max unit description t cycle 1 s minimum time between consecutive convst rising edges (excluding burst and oversampling modes) t conv_low 50 ns convst low pulse width t conv_high 50 ns convst high pulse width t busy_delay 3 4 ns convst high to busy high (manual mode) t cs _setup 20 ns busy falling edge to cs falling edge setup time t ch_setup 50 ns channel select setup time in hardware mode for chselx t ch_hold 20 ns channel select hold time in hardware mode for chselx t conv 475 530 ns conversion time for the selected channel pair t acq 470 ns acquisition time for the selected channel pair t quiet 50 ns cs rising edge to next convst rising edge t reset _low see figure 3 partial r eset 40 500 ns partial reset low pulse width full reset 1.2 s full reset low pulse width t device_setup see figure 3 partial reset 120 ns time between partial reset high and convst rising edge full reset 15 ms time between full reset high and convst rising edge t write see figure 3 partial reset 50 ns time between partial reset high and cs for write operation full reset 240 s time between full reset high and cs for write operation t reset _wait 1 ms time between stable v cc /v drive and release of reset (see figure 3 ) t reset _setup time prior to release of reset that queried hardware inputs must be stable for (see figure 3 ) partial reset 10 ns full reset 0.05 ms t reset _hold time after release of reset that latched hardware inputs must be stable for (see figure 3 ) partial reset 10 ns full reset 0.24 ms 1 not production tested. sample tested during initial release to ensure compliance. figure 2. universal timing diagram across all interfaces chsel0 to chsel2 cs busy convst ch x t ch_setup t ch_hold t cs_setup t acq t conv t conv_high t conv_low t cycle t busy_delay t quiet ch y hardware mode only 15695-002
data sheet ad7616- p rev. 0 | page 7 of 46 figure 3. reset timing diagram adc action chsel0 to chsel2 acq x conv x acq y conv y t reset_hold t write ch y ch x ch z hardware mode only all modes t reset_wait t device_setup t reset_setup t reset_low burst, seqen hw_rngsel0, hw_rngsel1 mode range setting in hw mode refsel cs busy convst reset v cc v drive 15695-003
ad7616- p data sheet rev. 0 | page 8 of 46 p arallel interface timing specifications table 3 . parameter min typ max unit description t cs _high 20 ns cs high pulse width t rd _setup 0 ns cs falling edge to rd falling edge setup time t rd _hold 0 ns rd rising edge to cs rising edge hold time t rd _high 20 ns rd high pulse width t rd _low 40 ns rd low pulse width t dout_setup 40 ns data access time after falling edge of rd t dout_3state 1 6 ns cs rising edge to db x high impedance t wr _setup 0 ns cs to wr setup time t wr _high 20 ns wr high pulse width t wr _low 40 ns wr low pulse width t wr _hold 0 ns wr hold time t din_setup 12 ns configuration data to wr setup time t din_hold 5 ns configuration data to wr hold time t conf_settle 2 0 ns configuration data settle time, wr rising edge to convst rising edge figure 4. parallel read timing diagram figure 5. parallel write timing diagram conv b conv a t rd_setup t dout_setup t rd_low t rd_high t cs_high t rd_hold t dout_3state cs rd busy db0 to db15 convst 15695-004 wr i t e r e g 1 write reg 2 t din_setup t din_hold t conf_settle t wr_high t wr_setup t wr_hold t wr_low cs wr db0 to db15 convst 15695-005
data sheet ad7616- p rev. 0 | page 9 of 46 absolute maximum rat ings t a = 25c, unless otherwise noted. table 4 . parameter rating v cc to agnd ?0.3 v to +7 v v drive to agnd ?0.3 v to v cc + 0.3 v analog input voltage to agnd 1 2 1 v digital input voltage to agnd ?0.3 v to v drive + 0.3 v digital output voltage to agnd ?0.3 v to v drive + 0.3 v refin out to agnd ?0.3 v to v cc + 0.3 v input current to any pin except supplies 1 10 ma operating temperature range ?40c to +125c storage temperature range ?65c to +150c junction temperature 150c soldering reflow pb/s n temperature (10 sec to 30 sec) 240 (+0)c pb - free temperature 260 (+0)c esd all pins except analog inputs 2 kv analog input pins only 8 kv 1 transient curren ts of up to 100 ma do not cause s ilicon c ontrolled r ectifier ( scr ) latch - up. stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extende d periods may affect product reliability. thermal resistance thermal performance is directly linked to printed circuit board ( pcb ) design and operating environment. close attention to pcb thermal design is required. ja is the natural convection junction to ambient thermal resistance measured in a one cubic foot sealed enclosure. jc is the junction to case thermal resistance. table 5 . thermal resistance package type ja jc unit st -80 -2 1 41 7.5 c/w 1 thermal impedance simulated values are based on a jedec 2s2p thermal test board. see jedec jesd51 . esd caution
ad7616- p data sheet rev. 0 | page 10 of 46 pin configuration an d function descripti ons figure 6. pin configuration table 6 . pin function descriptions pin no. type 1 mnemonic 2 description 1 ai gnd v4bgnd analog input ground for v4b . 2 ai v4b analog i nput channel 4, adc b. 3 ai gnd v5bgnd analog input ground for v5b . 4 ai v5b analog input channel 5 , adc b. 5, 16, 29, 72 p agnd analog supply ground . 6, 15, 30, 71 p v cc analog supply voltage, 4.7 v to 5.25 v. this supply voltage is applied to the internal front - end amplifiers and to the adc core. decouple t hese pins t o agnd using 0.1 f and 10 f capacitor s in parallel. 7 ai v6b analog input channel 6, adc b . 8 ai gnd v6bgnd analog input ground for v6b . 9 ai v7b analog input channel 7 , adc b. 10 ai gnd v7bgnd analog input ground for v7b . 11 ai gnd v7agnd analog input ground for v7a . 12 ai v7a analog input channel 7 , adc a. 13 ai gnd v6agnd analog input ground for v6a . 14 ai v6a analog input channel 6 , adc a. 17 ai v5a analog input channel 5, adc a . 18 ai gnd v5agnd analog input ground for v5a . 19 ai v4a analog input v4a. 20 ai gnd v4agnd analog input ground for v4 a . v4bgnd v4b v5bgnd v5b agnd v cc v6b v6bgnd v7b v7bgnd v7agnd v7a v6agnd v6a v cc agnd v5a v5agnd v4a v4agnd db12 db13 db14 db15 db11 db10 db9 db8 regcapd reggndd dgnd v drive db7 db6 db5 db3 db2 db1 db0 v3agnd v3a v2agnd v2a v1agnd v1a v0agnd v0a agnd v cc refcap refgnd refinout refinoutgnd refsel seqen hw_rngsel1 hw_rngsel0 v3bgnd v3b v2bgnd v2b v1bgnd v1b v0bgnd v0b agnd v cc regcap reggnd convst busy chsel2 chsel1 chsel0 AD7616-P top view (not to scale) reset par db4 wr/burst rd cs 2 3 4 7 6 5 1 8 9 10 12 13 14 15 16 17 18 19 20 1 1 59 58 57 54 55 56 60 53 52 51 49 48 47 46 45 44 43 42 41 50 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 analog input decoupling cap pin power supply ground pin digital input reference input/output digital input/output digital output 15695-006
data sheet ad7616- p rev. 0 | page 11 of 46 pin no. type 1 mnemonic 2 description 21 ai gnd v3agnd analog input ground for v3 a . 22 ai v3a analog input channel 3 , adc a. 23 ai gnd v2agnd analog input ground for v2a . 24 ai v2a analog input channel 2 , adc a . 25 ai gnd v1agnd analog input ground for v1a . 26 ai v 1 a analog input channel 1 , adc a . 27 ai gnd v0agnd analog input ground for v0 a . 28 ai v0a analog input channel 0 , adc a . 31 cap refcap referenc e buffer output force/sense . decouple t his pin to refgnd using a low effective series resistance ( esr ) , 10 f , x5r ceramic capacitor , as close to the refcap pin as possible . the voltage on this pin is typically 4.096 v. 32 gnd refgnd reference g round. connect t his pin to agnd. 33 ref refinout reference i nput/reference o utput. the on - chip voltage reference of 2.5 v is available on this pin for external use when the refsel pin is set to logic high. alternatively, the internal reference can be disabled by setting the ref s el pin to logic low, and an external reference of 2.5 v can be appl ied to this input. decoupling is required on this pin for both the internal and extern al reference options. connect a 100 nf, x7 r capacitor between the refinout and refinoutgnd pins, as close to the refinout pin as possible. if using an external reference, connect a 10 k series resistor to this pin to band limit the reference signal. 34 gnd refinoutgnd reference input, reference output g round. 35 di refsel internal/ e xternal r eference s election i nput. refsel is a l ogic input. if this pin is set to logic high, the internal reference is selected and enabled. if this pin is set to logic low, the internal reference is disabled and an external reference voltage must be applied to the refinout pin. the s ignal state is lat ched on the release of a full reset, and requires an additional full reset to reconfigure. 36 di reset reset input. connect a 100 pf capacitor between reset and ground. full and partial reset options are available. the type of reset is determined by the length of the reset pulse. keeping reset low places the device into shutdown mode. see the reset functionality section for further details. 37 di seqen channel sequencer enable input ( h ardware m ode o nly). when seqen is tied low, the sequencer is disabled. when seqen is high , the sequencer is enabled (with restricted functionality in hardware mode). see the sequencer section for further details. the signal state is latched on the release of a full reset, and requires an additional full reset to reconfigure. in software mode , this pin must be connected to dgnd. 38, 39 di hw_rngsel1, hw_rngsel0 hardware/ software mode selection, hardware mode range select inputs . hardware/software mode selection is latched at full reset. range selection in hardware mode is not latched. hw_rngsel x = 00 : s oftware mode ; the ad7616 -p is configured via the software registers. hw_rngselx = 01 : h ardware mode ; a nalog input range is 2.5 v. hw_rngselx = 10 : h ardware mode ; a nalog input range is 5 v. hw_rngselx = 11 : h ardware mode ; a nalog input range is 10 v. 40 di par pa rallel interface selection input. par is a lo gic input. this pin must be tie d to a logic low state on power - up or before the release of a full reset. par = 0: parallel interface selected. par = 1: invalid. 41 to 48 do/di db 0 to db7 parallel output/input data bit 0 to data bit 7 . t hese pins are output/input parallel data bits, db7 to db0. refer to the parallel interface section for further details. 49 p v drive logic power supply input. the voltage supplied at this pin (2.3 v to 3.6 v) determines the operating voltage of the interface. this pin is nominally at the same supply as the supply of the host interface. decouple this pin with 0.1 f and 10 f capacitor s in parallel. 50 gnd dgnd digital ground. this pin is the ground reference point for all digital circuitry on the ad7616 -p . the dgnd pin must connect to the dgnd plane of a system. 51 gnd reggndd ground for the d igital low dropout ( ldo ) regulator c onnected to regcapd ( p in 52). 52 cap regcapd decoupling capacitor pin for voltage output from the interna l digital regulator. decouple t his output pin separately to reggndd using a 10 f capacitor. the voltage at this pin is 1.8 9 v typical.
ad7616- p data sheet rev. 0 | page 12 of 46 pin no. type 1 mnemonic 2 description 53 to 60 do/di db8 to db15 parallel output/input data bit 8 to data bit 15 . t h e s e pin s act as three - state parallel digital input/output s . refer to the parallel interface section for further details. 61 di wr /burst write/burst mode enable. in software mode, this pin acts as wr for register write commands. in hardware mode, this pin enables burst mode. the signal state is latched on the release of a full reset, and requires an additional full reset to reconfigure. refer to the burst sequencer section for further information. 62 di rd parallel data read control input. when both cs and rd are logic low in parallel mode, the output bus is enabled. 63 di cs chip select. this active low logic input frames the data transfer. when both cs and rd are logic low, the dbx output bus is enabled and the conversion result is output on the parallel data bus lines. 64 to 66 di chsel 0 to chsel2 channel selection input 0 to input 2 ( hardware mode only ) . in hardware mode, these inputs select the input channels for the next conversion in adc a and adc b . for example, chselx = 0x000 select s v0a and v0b for the next conversion; chselx = 0x001 selects v1a and v1b for the next conversion . 67 do busy busy output. this pin transitions to a logic high after a convst rising edge and indicates that the conversion process started. the busy output remains high until the conversion process for the current selected channels is complete. the falling edge of busy signals that the conversion data is being latched into the output data registers and is available to read. data must be read after busy returns to low. rising edges on convst have no effect while the busy signal is high. 68 di convst conversion start input for adc a and adc b. this logic input initiate s conversions on the analog input channels. a conversion is initiated when convst transitions from low to high for the selected analog input pair. when burst mode and oversampling mode are disabled, every convst transition from low to high converts one channel pair. in sequencer mode, when burst mode or oversampling is enabled, a single convst transition from low to high is necessary to perform the required number of conversions. 69 gnd reggnd internal analog regulator ground. this pin must connect to the agnd plane of a system. 70 cap regcap decoupling capacitor pin for voltage output f rom internal analog regulator. decouple t his output pin separately to reggnd using a 10 f capacitor. the voltage at this pin is 1.8 7 v typical. 73 ai v0b analog input channel 0 , adc b. 74 ai gnd v0bgnd analog input ground for v0 b . 75 ai v1b analog input channel 1 , adc b. 76 ai gnd v1bgnd analog input ground for v1 b . 77 ai v2b analog input channel 2 , adc b. 78 ai gnd v2bgnd analog input ground for v2 b . 79 ai v3b analog input channel 3 , adc b. 80 ai gnd v3bgnd analog input ground for v3 b . 1 ai is analog input, gnd is ground, p is power supply, cap is decoupling capacitor pin, ref is reference input/output, di is digital input, and do is digital output. 2 note that throughout this data sheet, multifunction pins, such as wr /burst, are referred to either by the entire pi n name or by a single function of the pin, for example, wr , when only that function is relevant.
data sheet ad7616- p rev. 0 | page 13 of 46 typical performance characteristics v ref = 2.5 v internal, v cc = 5 v, v drive = 3.3 v, f sample = 1 msps, f in = 1 khz t a = 25 c, unless otherwise noted. figure 7. fast fourier transform ( fft ) , 10 v range figure 8. fft, 5 v range figure 9. fft burst mode, 10 v range figure 10 . snr vs. temperature figure 11 . sinad vs. temperature figure 12 . thd vs. temperature ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 0 40 60 80 100 magnitude (db) frequenc y (khz) snr = 90.44db sinad = 90.25db thd = ?103.41db n samples = 65536 15695-007 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 0 40 60 80 100 magnitude (db) frequenc y (khz) snr = 89.59db sinad = 89.39db thd = ?102.36db n samples = 65536 15695-008 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 10 0 20 30 40 50 magnitude (db) frequenc y (khz) snr = 90.6db sinad = 90.65db thd = ?107.4db n samples = 65536 15695-009 80 82 84 86 88 90 92 94 96 98 100 ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 125 snr (db) temper a ture (c) 10v range 5v range 2.5v range 15695-010 80 82 84 86 88 90 92 94 96 98 100 ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 125 sinad (db) temper a ture (c) 10v range 5v range 2.5v range 15695-0 1 1 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 125 thd (db) temper a ture (c) r source matched on vxx and vxxgnd inputs 10v range 5v range 2.5v range 15695-012
ad7616- p data sheet rev. 0 | page 14 of 46 figure 13 . typical inl error , 10 v range figure 14 . typical inl error, 5 v range figure 15 . typical dnl error, 10 v range figure 16 . typical dnl error, 5 v range figure 17 . dc histo gram of codes at code center, 10 v range figure 18 . dc hist ogram of codes at code center, 5 v range 0 10000 20000 30000 40000 50000 60000 in l error (lsb) code ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 15695-013 0 10000 20000 30000 40000 50000 60000 in l error (lsb) code ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 15695-014 0 10000 20000 30000 40000 50000 60000 dn l error (lsb) code ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 15695-015 0 10000 20000 30000 40000 50000 60000 code dn l error (lsb) ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 15695-016 29 32731 26334 2297 5 0 5000 10000 15000 20000 25000 30000 35000 32766 32767 32768 32769 32770 32771 number of hits code 10v range vxx and vxxgnd shorted together 65536 samples 4140 15695-017 36 3021 24343 31138 6841 157 0 5000 10000 15000 20000 25000 30000 35000 32764 32765 32766 32767 32768 32769 number of hits code 5v range vxx and vxxgnd shorted together 65536 samples 15695-018
data sheet ad7616- p rev. 0 | page 15 of 46 figure 19 . dc histo gram of codes at code center, 2.5 v range figure 20 . nfs error vs. temperature figure 21 . pfs error vs. temperature figure 22 . p fs/ n fs error vs. source resistance figure 23 . nfs/pfs error matching vs. temperature figure 24 . bipolar zero code error vs. temperature 1 85 2022 13596 27621 18123 249 2 1 0 5000 10000 15000 20000 25000 30000 32757 32758 32759 32760 32761 32762 32763 32764 32765 32768 number of hits code 2.5v range vxx and vxxgnd shorted together 65536 samples 3836 15695-019 ?30 ?20 ?10 0 10 20 30 ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 125 nfs error (lsb) temper a ture (c) 10v range 5v range 2.5v range 15695-020 ?30 ?20 ?10 0 10 20 30 ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 125 pfs error (lsb) temper a ture (c) 10v range 5v range 2.5v range 15695-021 0 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 0.009 0 20 40 60 80 100 p fs /n fs e rror ( % fs ) s o u rc e re s i s t an c e ( k ) n f s 10v range n f s 5v range n f s 2.5v range p f s 10v range p f s 5v range p f s 2.5v range 15695-022 ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 125 temper a ture (c) 0 1 2 3 4 5 6 7 8 9 10 nfs/pfs error m a tching (lsb) pfs 10v range nfs 10v range 15695-023 -10 -8 -6 -4 -2 0 2 4 6 8 10 bipolar zero code error (lsb) ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 125 temper a ture (c) 10v range 5v range 2.5v range 15695-024
ad7616- p data sheet rev. 0 | page 16 of 46 figure 25 . bipolar zero error matching vs. temperature figure 26 . thd vs. input frequency for various source impedances, 10 v range figure 27 . thd vs. input frequency f or various sou r ce impedances, 5 v range figure 28 . snr vs. input frequency for d ifferent oversampling rates, 10 v range figure 29 . snr vs. input frequency for d ifferent oversampling rates, 5 v range figure 30 . channel to channel isolation vs. interferer frequency 0 1 2 3 4 5 6 7 8 ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 125 bipolar zero error m a tching (lsb) temper a ture (c) dc input 10v range 5v range 2.5v range 15695-025 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 1k 10k 100k t h d ( d b ) i npu t f r e qu e n c y ( h z ) 0 50 100 1.2k 5.6k 10k 23.7k 47.3k 105k 10v range r source matched on vxx and vxxgnd inputs 15695-026 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 1k 10k 100k t h d ( d b ) i npu t f r e qu e n c y ( h z ) 0 50 100 1.2k 5.6k 10k 23.7k 47.3k 105k 5v range r source matched on vxx and vxxgnd inputs 15695-027 100 1k 10k 100k snr (db) input frequency (hz) n o o s o s r 2 o s r 4 o s r 8 o s r 16 o s r 32 80 82 84 86 88 90 92 94 96 98 10v range 15695-028 100 1k 10k 100k snr (db) input frequency (hz) n o o s o s r 2 o s r 4 o s r 8 o s r 16 o s r 32 80 82 84 86 88 90 92 94 96 98 5v range 15695-029 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 0 5000 10000 15000 20000 25000 30000 channe l t o channe l isol a tion (db) interferer frequenc y (hz) 10v range 5v range 2.5v range 15695-030
data sheet ad7616- p rev. 0 | page 17 of 46 figure 31 . phase delay vs. temperature figure 32 . internal reference voltage vs. temperature for various supply voltages figure 33 . analog input current vs. temperature for various supply voltages figure 34 . psrr vs. ripple frequency figure 35 . cmrr vs. ripple frequency figure 36 . static/dynamic i vcc current vs. temperature 0 2 4 6 8 10 12 ?40 ?25 ?10 5 20 35 50 65 80 95 110 125 p h as e d e l a y ( s ) t e m p e r a t u r e (c) 10v range 5v range 2.5v range 15695-031 2.490 2.495 2.500 2.505 2.510 ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 125 interna l reference vo lt age (v) temper a ture (c) 4.75v 5v 5.25v 15695-032 ?15 ?10 ?5 0 5 10 15 ?40 ?25 ?10 5 20 35 50 65 80 95 110 125 analog input current (a) temperature (c) + 10 v i n p u t ?10 v i n p u t + 5v i n p u t ?5 v i n p u t + 2.5 v i np u t ?2.5 v i n p u t 15695-033 40 50 60 70 80 90 100 110 120 130 0.1 1 10 100 1000 psrr (db) ripple frequenc y (khz) 10v range 5v range 2.5v range 100mv p-p sine wave applied to v cc supply 15695-034 ?120 ?100 ?80 ?60 ?40 ?20 0 10 100 1k 10k 100k 1m 10m cmrr (db) ripple frequenc y (hz) 10v range 5v range 2.5v range 15695-035 0 10 20 30 40 50 60 70 80 90 100 ?40 ?25 ?10 5 20 35 50 65 80 95 110 125 temperature (c) static/dynamic i vcc current (ma) static dynamic 15695-036
ad7616- p data sheet rev. 0 | page 18 of 46 figure 37 . dynamic v drive current vs. temperature figure 38 . static v drive current vs. temperature figure 39 . i vcc current vs. sampling frequency 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 ?40 ?25 ?10 5 20 35 50 65 80 95 110 125 dynamic v drive current (ma) temperature (c) 15695-071 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 ?40 ?25 ?10 5 20 35 50 65 80 95 110 125 static v drive current (ma) temperature (c) 15695-070 38 39 40 41 42 43 44 45 46 47 100 200 300 400 500 600 700 800 900 1000 i vcc current (ma) sampling frequenc y (ksps) 15695-039
data sheet ad7616- p rev. 0 | page 19 of 46 terminology integral nonlinearity (inl) inl is t he maximum deviation from a straight line passing through the endpoints of the adc transfer function. the endpoints of the transfer function are zero scale, a t ? lsb below the first code transition ; and full scale , at ? lsb above the last code transition. differential nonlinearity (dnl) dnl is t he difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. bipolar zero code error bipolar zero code error is th e deviation of the midscale transition (all 1s to all 0s) from the ideal , which is 0 v ? ? lsb. bipolar zero code error match ing bipolar zero code error match ing is t he absolute difference in bipolar zero code error between any two input channels. positive full - scale (pfs) error pfs error is t he deviation of the actual last code transition from the ideal last code transition (10 v ? 1 ? lsb (9.999 54), 5 v ? 1 ? lsb ( 4.99977 ) , and 2.5 v ? 1? lsb ( 2 .4 998 9) ) after bipolar zero code error is adjusted out. the pfs error includes the contribution from the internal reference buffer. pfs error match ing pfs error match ing is th e absolute difference in positive full - scale error between any two input channels. negative full - scale (nfs) error nfs error is t he deviation o f the first code transition from the ideal first code transition ( ? 10 v + ? lsb ( ? 9.999 8 5 ) , ? 5 v + ? lsb ( ? 4.99992) and ? 2.5 v + ? lsb ( ? 2.49996) ) after the bipolar zero code error is adjusted out. the nfs error includes the contribution from the internal reference buffer. nfs error match ing nfs error match ing is t he absolute difference in negative full - scale error between any two input channels. signal -to - noise - and - distortion ratio (sinad) sinad is the me asured ratio of signal to noise and distortion at the output of the adc. the signal is the rms value of the sine wave, and noise is the rms sum of all nonfundamental signals up to half the sampling frequency (f s /2), including harmonics, but excluding dc. signal -to - noise ratio (snr) snr is the measured ratio of signal to noise at the output of the adc. the signal is the rms amplitude of the fundamental. nois e is the sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent on the number of quantization levels in the digitization process: the greater the number of levels, the smaller the quantization noise. the theoretical snr for an ideal n - bit converter with a sine wave input is given by snr = (6 .02 n + 1.76) db where n is the number of bits. therefore, for a 16 - bit converter, the snr is 98 db. total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic components to the rms value of a full - scale input signal and is expressed in decibels (db). peak harmonic or spurious noise peak harmonic or spurious noise t he ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2, excluding dc) to the rms value of the fundamental. normally, the value of this specification is determined by the largest harmonic in the spectrum, but for adcs where the harmonics are buried in the noise floor, it is determined by a noise peak. intermodulation distortion (imd) with inputs consisting of sine waves at t wo frequencies, fa and fb, any active device with nonlinearities create s distortion products at the sum and difference frequencies of mfa nfb, where m , n = 0, 1, 2, 3. intermodulation distortion terms are those for which neither m nor n is equal to 0. fo r example, the second - order terms include (fa + fb) and (fa ? fb), and the third - order terms include (2fa + fb), (2fa ? fb), (fa + 2fb), and (fa ? 2fb). the calculation of the intermodulation distortion is per the thd specification, where it is the ratio o f the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels (db) . power supply rejection ratio (psr r ) variations in power supply affect the full - scale transition but not the linearity of the converter . power supply rejection is the maximum change in full - scale transition point due to a change in power supply voltage from the nominal value. the psrr is defined as the ratio of the power in the adc output at full - scale frequency, f, to the po wer of a 1 00 mv p - p sine wave applied to the v cc supply of the adc of f requency , f s . psrr (db) = 10log( pf / pf s ) where: pf is equal to the power at f r equency , f , in the adc output. pf s is equal to the power at f requency , f s , coupled onto the v cc supply.
ad7616- p data sheet rev. 0 | page 20 of 46 ac common - mode rejection ratio (ac cmrr) ac cmrr is defined as the ratio of the power in the adc output at frequency, f, to the power of a sine wave applie d to the common - mode voltage of vx x and vx x gnd at frequency, f s . ac cmrr (db) = 10log( pf / pf s ) where: pf is the power at frequency, f, in the adc output. pf s is the power at frequency, f s , in the adc output. channel to channel isolation channel to channel isolation is a measure of the level of crosstalk between all input channels. it is me asured by applyi ng a full - scale sin e wave signal , up to 160 khz, to all unselected input channels and then determining the degree to which the signal attenuates in the selected channel with a 1 khz sine wave signal applied . phase delay phase delay is a measure of the absolute time delay between when an analog input is sampled by the converter and when the result associated with that sample is available to be read back from the adc, including delay induced by the analog front end of the d evice. phase delay drift phase delay drift is the change in phase delay per unit temperature across the entire operating temperature of the device. phase delay matching p hase delay matching is the maximum phase delay seen between any simultaneously sampled pair.
data sheet ad7616- p rev. 0 | page 21 of 46 theory of operation converter details the ad7616 - p is a das that employs a high speed, low power, charge redistribution, sar adc , and allow s dual simultane ous sampling of 16 analog input channels. the analog inputs on the ad7616 - p can ac cept true bipolar input signals. analog input range options include 10 v, 5 v , and 2.5 v. the ad7616 - p operate s from a single 5 v supply. the ad7616 - p c ontain s input clamp protection, input signal scaling amplifiers, a first - order antialiasing filter, an on - c hip reference, a reference buffer , a dual high speed adc, a digital fil ter , a flexible sequencer , and a high speed parallel interface. the ad7616 - p can be operated in hardware or software mode by controlling the hw_rngselx pins. in hardware mode , the ad7616 - p is configured by pin control. in software mode , the ad7616 - p is configured by the control registers accessed via the parallel interface. analog input analog input channel selection the ad7616 - p contains dual , simultaneous sampling , 16 - bit adcs. each adc has eight analog input channels for a total of 16 analog input channels. additionally , the ad7616 - p has on - chip diagnostic chann els to monitor the v cc supply and an on - chip adjustable ldo regulator . channels can be selected for conversion by using th e chselx pins in hardware mode or via the channel register control in software mode. software mode is required to sample the diagnostic channels. channels can be selected dynami - cally or the ad7616 - p has an on - chip sequencer to allow the channels for conversion to be preprogrammed. in hardware mode , simul taneous sampling is limited to the corresponding adc a and adc b analog input channel s. for example, channel v 0 a is always sampled with channel v0 b . in software mode , it is possible to select any adc a channel with any adc b channel for simultaneous sampli ng. analog input ranges the ad7616 - p can handle true bipolar, single - ended input voltages. the logic level s on the range select pins, hw_rngsel 0 and hw_rngsel1 , determine the analog input range of all analog input channels. if both range select pins are tied to a logic low, the analog input range is determined in software mode via the input range r egisters ( see the register summary section for more details ) . in software mode, it is possible to configure an individual analog input range per channel. table 7 . analog input range selection analog input range hw_rngsel 1 hw_rngsel 0 configured via the input range registers 0 0 2.5 v 0 1 5 v 1 0 10 v 1 1 in hardware mode, a logic change on th ese pin s has an imme diate effect on the analog input range; however , there is typically a settling time of approximately 120 s in addition to the normal acquisition time requirement. the recommended practice is to hardwire the range select pin s according to the desired input range for the system signals. analog input impedance the analog input impedance of the ad7616 - p is 1 m? , a fixed input impedance tha t does not vary with the ad7616 - p sampling frequency. this high analog input impedance eliminates the need for a driver amplifier in front of the ad7616 - p , allowing direct connection to the source or sensor. analog input clamp protection figure 40 shows the analog input circuitry of the ad7616 - p . each analog input of the ad7616 - p contains clamp protection circuitry. despite single 5 v supply operation, this analog input clamp protection allows an input overvoltage of between ?20 v and +20 v . figure 40 . analog input circuitry figure 41 shows the input clamp current vs. source voltage characteristic of the clamp circuit. for source voltages between ? 20 v and +20 v , no current flows in the clamp circuit. for input voltages th at are greater than + 2 0 v and less than ?20 v , the ad7616 - p clamp circuitry turns on. figure 41 . input protection clamp profile , input clamp current vs. source voltage place a series resistor on the analog input channels to limit the current to 10 ma for input voltages greater than + 2 0 v and less than ?20 v . in an application where there is a series resistance on an analog input, v x a or vx b , a corresponding resistance is required on the analog input ground channel, v x a gnd or vx b gnd (see figure 42 ). if there is no correspond ing resistor on 1m? clamp vxx 1m? clamp vxxgnd first- order lpf r fb r fb 15695-040 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 0.25 ?30 ?20 ?10 0 10 20 30 input clam p current (ma) source vo lt age (v) powered off powered on 15695-041
ad7616- p data sheet rev. 0 | page 22 of 46 the v x a gnd or v x b gnd channel, an offset error occurs on that channel. use the input overvoltage clamp protection circuitry to protect the ad7616 - p against transient overvoltage events. it is not recommended to leave the ad7616 - p in a condition where the clamp protection circuitry is active in normal or power - down conditions for extended periods . figure 42 . input resistance matching on the analog input analog input antialiasing filter a n analog antialia sing filter ( first - order butterworth) is also provided on the ad7616 - p . figure 43 and figure 44 show the frequency and phase response, respectively, of the analog antialiasing filter. the typical corner frequency in the 10 v range is 39 khz, and 33 khz in the 5 v range. figure 43 . analog antialiasing filter frequency response figure 44 . analog antialiasing filter phase response adc transfer functio n the output coding of the ad7616 - p is twos complement. the designed code transi tions occur midway between successive integer lsb values, that is, 1/2 lsb and 3/2 lsb. the lsb size is full - scale range 65,536 for the ad7616 - p . the ideal transfer characteristic s for the ad7616 - p are shown in figur e 45. the lsb size is dependent on the analog input range selected. figure 45 . transfer characteristics internal/eternal re feren ce the ad7616 - p can operate with either an internal or external reference. the device contains an on - chip , 2.5 v band gap refer - ence. the refinout pin allows access to the 2.5 v reference that generates the on - chip 4.096 v reference internally, or it allows an external r eference of 2.5 v to be applied to the ad7616 - p . an externally applied reference of 2.5 v is also amplified to 4.0 96 v using the internal buffer. this 4.096 v buffered reference is the reference used by the sar adc. the refsel pin is a logic input pin tha t allows the user to select between the in ternal reference and an external reference. if this pin is set to logic high, the internal reference is selected and enabled. if this pin is set to logic low, the internal reference is disabled and an external refe rence voltage must be applied to the refinout pin. the internal reference buffer is always enabled. after a full reset , the ad7616 - p operates in the reference mode selected by the ref sel pin. decoupling is required on the refinout pin for both the internal and external reference options. a 100 nf , x8r ceramic capacitor is required on the refinout pin to refinoutgnd. the ad7616 - p contains a reference buffer configured to amplify the reference v oltage to ~4.096 v. a 10 f , x5r ceramic capacitor is required between refcap and refgnd. the reference voltage available at the refinout pin is 2.5 v. when the ad7616 - p is configured in external reference mode, the refinout pin is a high input impedance p in. 1m? clamp vxx 1m? clamp vxxgnd r fb r fb c r r analog input signal AD7616-P 15695-042 ?30 ?25 ?20 ?15 ?10 ?5 0 5 100 1k 10k 100k a ttenu a tion (db) input frequenc y (hz) 10v range 5v range 2.5v range 15695-043 0 1 2 3 4 5 6 100 1k 10k 100k p ha s e ( s ) i n p u t fr e qu e n c y ( hz) 10v range 5v range 2.5v range 15695-044 011 . . . 11 1 011 . . . 11 0 000 . . . 00 1 000 . . . 00 0 111 . . . 11 1 100 . . . 01 0 100 . . . 00 1 100 . . . 00 0 ? f s + 1 / 2 l s b 0 v ? 1 / 2 l s b + f s ? 3 / 2 l s b a dc c o d e an a l og i n p u t + f s m i d s ca l e ? f s l s b 10 v ra n g e + 1 0 v 0 v ?10 v 3 05 v 5 v r a n g e + 5 v 0 v ?5v 1 52 v 2.5 v r a n g e + f s ? ( ? f s ) 2 n * *where n is the number of bits of the converter l s b = v in 5 v 2.5v refinout 5 v c o d e = 32 , 7 68 v in 2.5 v 2.5v refinout 2.5 v c o d e = 32 , 7 68 v in 10 v 2.5v refinout 10v c o d e = 32, 7 68 + 2.5 v 0 v ?2.5 v 76 v 15695-045
data sheet ad7616- p rev. 0 | page 23 of 46 if the internal reference is to be applied elsewhere within the system , i t must first be buffered externally. figure 46 . reference circuitry shut d own m ode the ad7616 - p enter s shutdown m ode by keeping the reset pin low for greater than 1.2 s. when the reset pin is set from low to high , the device exit s shutdown mode and enter s normal mode. when the ad7616 - p is placed in shutdown mode, the current consumption is typically 78 a and the power - up time to perform a write to the device is approximately 240 s . the p ower - up time to perform a conversion is 15 ms. in shut down mode , all circuitry is powered down and all registers are cleared and reset to their default values. digital filter the ad7616 - p contains an optional digital , first - order sinc filter for use in applications where slower throughput rates are in use or where higher snr or dynamic range is desirable. the osr of the digital filter is controlled in software via the os bits in the c onfi guration r egister . in software mode, over - sampling is enabled for all channels after the os bits are set in the c onfiguration r egister . table 8 provides the oversampling bit decoding to select the different oversample rates. in addition to the oversampling function, the output result is decimated to 16 - bit resolution. if the os bits are set to select an os r of eight, the next convst rising edge takes the first sample for the selected channel, and the remaining seven samples for that chan nel are taken with an internally generated sampling signal. these samples are then averaged to yiel d an improvement in snr performance. as the os ratio increases, the ?3 db frequency is reduced, and the allowed sampling frequency is also reduced. t he conversion time extends as the oversampling rate is increased, and the busy signal scales with oversampl ing rates. acquisition and conversi on time increase linearly with the osr . if oversampling is enabled with the sequencer or in burst mode, the extra samples are gathered for a given channel before the sequencer moves on to the next channel. table 8 shows the typical snr performance of the device for each permissible osr . the input tone used is a 100 hz sine wave for the three input ranges of the device. a plot of snr vs. osr is shown in figure 47. figure 47 . typical snr vs. osr for all analog input ranges table 8 . oversampling bit decoding os bits osr typical snr (db) ? 3 db bandwidth (khz), all ranges 2.5 v range 5 v range 10 v range 000 no oversampling 87.5 89.7 90.8 37 001 2 88.1 90.6 91.8 36.5 0 10 4 89 91.6 92.9 35 0 11 8 89.9 92.6 93.9 30.5 100 16 91 93.6 94.9 22 101 32 92.6 94.8 95.8 13.2 110 64 93.9 95.5 96.2 7.2 111 128 94.4 95.4 95.9 3.6 buf 2.5v ref refinout refsel refinoutgnd refinoutgnd refcap 100nf 10f 15695-046 97 96 95 94 93 92 91 90 89 88 87 0 20 40 60 80 100 snr (db) osr 2.5v range 5v range 10v range f in = 100hz 120 15695-047
ad7616- p data sheet rev. 0 | page 24 of 46 applications informa tion functionality overvi ew the ad7616 - p has two main modes of operation : hardware mode and software mode . depending on the mode of operation , certain functionality may not be available. full functionality is available in software mode ; restricted functionality is available in hardware mode. table 9 shows the functionality available in the different modes of operation. table 9 . available functionality functionality operation mode 1 software mode (hw_rngselx = 00) hardware mode (hw_rngselx 00) internal/external reference yes yes selectable analog input ranges individual channel configuration yes no common channel configuration no yes sequential sequencer yes yes fully configurable sequencer yes no burst mode yes yes on - chip oversampling yes no cyclic redundancy check (crc) yes no diagnostic channel conversion yes no hardware reset yes yes register access yes no 1 yes means available; no means not available. power supplies the ad7616 - p has two independent power supplies, v cc and v drive , that supply the analog circuitry and digital interface , respectively. decouple both t he v cc supply and the v drive supply with a 10 f capacitor in parallel with a 100 nf capacitor. additionally , these supplies are regulated by two internal ldo regulators. the analog ldo (aldo) typically supplies 1.8 7 v . decouple the aldo with a 10 f capacitor between the regcap and reggnd pins. the digital ldo (dldo) typically supplies 1.89 v . decouple the dldo with a 10 f capacitor between the regcapd and reggndd pins. the ad7616 - p is robust to power supply sequencing. the recom - mended sequence is to power up v drive first , followed by v cc . hold reset low until both supplies are stabilized. typical connections figure 48 shows the typical connections required for correct operation of the ad7616 - p . decouple t he v cc and v drive supplies as shown in figure 48. place t he sm aller, 0.1 f capacitor as close to the supply pin as possible, with the larger , 10 f bulk capacitor in parallel. decouple t he reference and ldo regulators as shown in figure 48 and as described in table 6 . the analog input pins require a matched resistance, r, on both the vxa and vxagnd (similarly , vxb and vxbgnd) inputs to avoid a gain error on the analog input channels caused by an impedance mismatch. figure 48 . typical external connections adc adc pga pga buf 2.5v ref aldo dldo r r r r c c 10f x5r 0.1f x8r refinout refinoutgnd refcap refgnd v cc v drive 5v 2.5v/3.3v 10f 10f 0.1f 0.1f 10f 10f AD7616-P regcap reggnd regcapd reggndd vxa vxagnd vxbgnd vxb mux mux 15695-048
data sheet ad7616- p rev. 0 | page 25 of 46 device configuration operational mode the mode of operation, hardware mode or software mode , is configured when the ad7616 - p is released from full reset . the logic level of the hw_rngselx pins when the reset pin t ransitions from low to high determines the operational mode. the hw_rngselx pins are dual function. if hw_rngselx = 0b00 , the ad7616 - p enter s software mode. any other combination of the hw_rngselx configure s the ad7616 - p to hardware mode and the analog input range is configured as per table 7 . after software mode is configured , the logic level of the hw_rngselx si gnals is ignored. after an operation al m ode is configured , a full reset via the reset pin is required to exit the operation al mode and to set up an alternative mode. if hardware mode is selected , all further device configuration is via pin control. access to the on - chip registers is prohibited in hardware mode. in software mode , the interface and referenc e configuration must be config - ured via pin control , but all further device configuration is via register access only . internal / external reference the internal reference is enabled or disabled when the ad7616 - p is released from a full reset . the logic lev el of the refsel signal when the reset pin transitions from low to high configures the reference. after the reference is configured , changes to the logic level of the refsel signal are ignored. if the refsel signal is set to 1 , the internal reference is enabled. if refsel is set to l ogic 0 , the internal reference is disabled and an external reference must be supplied to the refinout pin for correct operation of the ad7616 - p . a full reset via the reset pin is re quired to exit the operation al mode and set up an alternative mode. connect a 100 nf capacitor between the refinout and refinoutgnd pins. if using an external reference, place a 10 k band limiting resistor in series between the reference and the refinout pin of the ad7616 - p . hardware mode if hardware mode is selected , the available functionality is restricted and all functionality is configured via pin control. the logic level of the following signals is checked after a full reset to configure the function ality of the ad7616 - p : crc, burst, and seqen. table 10 provides a summary of the signals that are latched by the device on the release of a full reset, depending on the mode of operation chosen. after the device is configured , a full reset via th e reset pin is required to exit the configuration and set up an alternative configuration. the chselx pins are r ead at reset to determine the initial a nalog input channel pair to acquire for conversion or to configure the initial settings for the sequencer. the channel pair selected for conversion or the hardware sequencer can be reconfigured during normal operation by setting and maintaining the chselx signal level before the convst rising edge until the busy falling e dge. the hw_rngselx signals control the analog input range for all 16 analog input channels. a logic change on these pins has an imme diate effect on the analog input range; however, the typical settling time is approximately 120 s, in addition to the norm al acquisition time requirement , t acq . the recommended practice is to hardwire the range select pins according to the desired input range for the system signals. access to the on - chip registers is prohibited in hardware mode. table 10. summary of l atched h ardware s ignals 1 signal latched at full reset read at reset read d uring busy edge driven hw mode sw mode hw mode sw mode hw mode sw mode hw mode sw mode refsel yes yes n/a n/a n/a n/a n/a n/a seqen yes no n/a n/a n/a n/a n/a n/a hw_rngselx (range change) n/a n/a yes yes n/a n/a yes no hw_rngselx (h ardware (hw) or software ( sw ) m ode) yes yes n/a n/a n/a n/a n/a n/a par yes yes n/a n/a n/a n/a n/a n/a burst yes no n/a n/a n/a n/a n/a n/a chselx n/a n/a yes no yes no n/a n/a 1 blank cells in table 10 mean not applicable.
ad7616- p data sheet rev. 0 | page 26 of 46 software mode if software mode is selected and the reference is configured, all other configuration settings in the ad7616 - p are controlled via the on - chip registers. all functionality of the ad7616 - p is available when software mode is selected. table 10 provides a summary of the signals that are latched by the device on the release of a full reset, depending on the mode of ope ration chosen. r eset functionality the ad7616 - p has two reset modes: full or partial . the reset mode selected is dependent on the length of the reset low pulse. a partial reset requires the reset pin to be held low between 40 ns and 500 ns. after 120 n s from the release of reset , the device is fully functional and a conversion can be initiated . a full reset requires the reset pin to be held low for a minimum of 1.2 s. after 1 5 m s from the release of reset , the device is completely reconfigure d and a conversion can be init i ated. a partial reset reinitializes the following modules: ? sequencer ? digital f ilter ? both sar adcs the current conversion result is discarded on completion of a partial reset. the partial reset does not affect the register values programmed in software mode or the latches that store the user configuration in both hardware and software modes. a dummy conversion is required in software m ode after a partial reset. a full reset returns the device to its default power - on state. the following fe atures are configured when the ad7616 - p is released from full reset : ? hardware m ode or s oftware m ode ? internal/ e xternal r eference ? i nterface ty pe on powe r - up , the reset signal can be released as soon as both the v cc and v drive supplies are stable. t he logic level of the hw_rngselx , refsel, and pa r pins when the reset pin is released after a full reset determine s the configuration. if hardware mode is selected , the functionality determined by the burst and seqen signals is also latched when the reset pin transitions from low to high in full reset mode , as shown in figure 3 . after the functionality is configured, changes to these signals are ignored. in hardware mode, the analog input range ( hw_rngselx signals) can be configured during a full reset, a partial reset , or during normal operation, but hardware/software mode selection requires a full reset to reconfigure when latched. in hardware mode , the chselx and hw_rngsel x pins are r ead upon release of a full or partial reset to perform the following actions: ? determine t he initial analog input channel pair to acquire for conversion . ? c onfigure the init ial settings for the sequencer . ? select the analog input voltage range . the chselx and hw_rngselx signals are not latched. the chann el pair selected for conversion , or the hardware sequencer , can be reconfigured during normal operation by setting and maintaining the chselx signal level before the convst rising edge , and ensuring the signal level remains constant until after busy transi tions low again. see the channel selection section for further details. in software mode , all additional functionality is configured by controlling the on - chip registers. pin function overvie w there are several dual - function pins on the ad7616 - p . their functionality is dependent on the mode of operation selected by the hw_rngselx pins. table 11 outlines the pin functionality in the different modes of operation and interface modes. table 11 . pin functionality overview pins operation mode software (hw_rngselx = 00) hardware (hw_rngselx 00) chselx no function, connect to dgnd chselx rd rd rd wr /burst wr burst db15 to db0 db15 to db0 db15 to db0 hw_rngselx hw_rngselx, connect to dgnd hw_rngselx, configure analog input range seqen no function, connect to dgnd seqen refsel refsel refsel
data sheet ad7616- p rev. 0 | page 27 of 46 digital interface channel selection hardware mode the logic level of the chselx signals determine s the channel pair for conversion; s ee table 12 for signal decoding information. the chselx signals at the time that either full or partial reset is released determine the initial channel pair to sample. after a reset , the logic levels of the chselx signals are examined during the busy high period to set the channel pair for the next conversion. the chselx signal level m ust be set before convst goes from low to high and must be maintained until busy goes from high to low to indicate a conversion is complete. see figure 49 for further details. software mode in software mode , the channels for conversion are selected using the c hannel r egister . on power - up or after a reset , the default channels selected for conversion are analog input v 0 a and analog input v0 b . table 12. chselx pin decoding channel selection input pin analog input s for conversion ch sel 0 ch sel 1 ch sel 2 0 0 0 v 0 a , v0 b 0 0 1 v1 a , v1 b 0 1 0 v2 a , v2 b 0 1 1 v3 a , v3 b 1 0 0 v4 a , v4 b 1 0 1 v5 a , v5 b 1 1 0 v6 a , v6 b 1 1 1 v7 a , v7 b figure 49 . hardware mode channel conversion setting figure 50 . software mode channel conversion setting reset convst busy ch x a/b x a/b y a/b z ch y ch z ch... chsel2 to chsel0 data bus configure point configure point configure point initial setup 15695-050 reset convst busy cs wr rd ch x a 0 b 0 ch y a x b x ch z a y b y ch db0 to db15 chx conversion start 15695-051
ad7616- p data sheet rev. 0 | page 28 of 46 parallel interface the parallel interface read s the conversion results and , in software mode , config ure s / read s back the on - chip registers . data can be read from the ad7616 - p via the parallel data bus with standard cs , rd , and wr signals. reading conversion results the convst signal initiate s the conversion process. a low to high transition on the convst signal initiates a conversion of the selected inputs. the busy signal goes high to indicate a convers ion is in progress. when the busy signal transitions from high to low to indicate that a conversion is complete , it is possible to read back conversion results on the parallel interface. data can be read from the ad7616 - p via the parallel data bus with standard cs and rd signals. the cs and rd input signals are internally gated to enable the conversion result onto the data bus. the data lines, db15 to db0, leave their high impedance state when both cs and rd are logic low. the rising edge of the cs input signal three - states the bus, and the falling edge of the cs input signal takes the bus out of the high impedance state. cs is the control signal that enables the data lines; it is the function that allows multiple ad7616 - p devices to share the same parallel data bus. the number of required read operations depends on th e device configuration. a minimum of two reads are required to read the conversion result for the simultaneously sampled adc a and adc b channels. if additional functions such as crc, status , and b urst mode are enabled , the number of required read backs inc reases accordingly. t he rd pin read s data from the output conversion results register. applying a sequence of rd pulses to the rd pin of the ad7616 - p clocks the conversion results out from each c hannel onto the parallel bus , db 15 to db 0. the first rd falling edge after busy goes low clocks out the conversion result from adc a . the next rd falling edge updates the bus with the adc b conversion result. writing register data in software mode , a ll the read/write registers in the ad7616 - p can be written to over the parallel interface. a register write command is performed by a single 16 - bit parallel access via the p arallel bus ( db15 to db0 ) , cs , and wr signals. provide d ata written to the ad7616 - p on the db 15 t o db0 inputs, with db0 as the lsb of the data - word. the format for a write command is shown in figure 51 . bit d15 must be set to 1 to select a write com - mand. bits[d14:d9] contain the re gister address , regaddr[5:0] . the subsequent nine bits (bits[d8: d 0]) contain the data to be written to the selected register. see the register summary section for the complete list of register addresses. data is latched into the device on the rising edge of wr . figure 51 . parallel interface register write reading register data all the registers in the device can be read over the parallel interface. a register read is performed by first writing the address of the register to be read to the ad7616 - p . the format for a register read command is shown in figure 53 . bit d15 must be set to 0 to select a read command. bits[d14:d9] co ntain the register addres s. the subsequent nine bits (bits[d8: d 0]) are ignored. the read command is latched into the ad7616 - p on the rising edge of wr . this latch transfers the relevant register data to the output register. the register d ata can then be read on the db15 to db 0 pins by using a standard read command. see figure 53 for additional information. figure 52 . parallel interface conversion readback cs wr write reg 1 write reg 2 db15 to db0 15695-052 convst busy cs rd conv a conv b db15 to db0 15695-053
data sheet ad7616- p rev. 0 | page 29 of 46 figure 53 . parallel interface register read table 13. write command message configuration msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 w / r regaddr[5:0] data[8:0] 1 register address data to write table 14. read command message configuration msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 w / r regaddr[5:0] data[8:0] 0 register address do not care cs wr rd read reg 1 data reg 1 read reg 2 data reg 2 db15 to db0 15695-054
ad7616- p data sheet rev. 0 | page 30 of 46 sequencer the ad7616 - p features a highly configurable on - chip sequencer. the functionality and configuration of the sequencer is dependent on the mode of operation of the ad7616 - p . in h ardware m ode , the sequencer is sequential only . the sequencer always start s converting at analog input v 0 a and analog input v 0 b and convert s each subsequent channel up to the configured end channel. in s oftware m ode , the sequencer has additional functionality and configurability . the sequencer stack has 32 uniquely configurable sequence steps , allowing any channel order to be programmed . additionally, any vxa analog input can be paired with any vxb analog input or diagnostic channel. th e sequencer c an be operated with or without the b urst function enabled. with the burst function enabled , only one convst pulse is required to convert every channel in a sequence. with burst mode disabled , one convst pulse is required for every conversion s tep in the sequence. see the burst sequencer section for additional details on operating in burst mode. hardw are mode sequencer in h ardware m ode , the sequencer is controlled by the seqen pin and the chselx pins. the sequencer is enabled or disabled when the ad7616 - p is released from full reset . the logic level of the seqen pin when the reset pin is released determines whether the sequencer is enabled or disabled ( see table 15 for settings ) . after the reset pin is released , the function is fixed and a full rese t via the reset pin is required to exit the function and set up an alternative configuration . table 15. hardware mode sequencer configuration seqen interface mode 0 sequencer disabled 1 sequencer enabled when t he sequencer is enabled , the logic levels of the chselx pins determine the final channel pair of the sequence . the chselx pins at the time reset is release d determine the initial settings for the channels to convert in the sequence. to reconfigure the channels selected for conversion thereafter , set the chselx pins to the required setting for the duration of the final busy pulse before the current conversion sequence is complete. see figure 54 for further details. table 16. chsel x pin decoding sequencer channel selection input pin analog input s for sequential conversion ch sel 0 ch sel 1 ch sel 2 0 0 0 v0 x only 0 0 1 v0 x to v1 x 0 1 0 v0 x to v2 x 0 1 1 v0 x to v3 x 1 0 0 v0 x to v4 x 1 0 1 v0 x to v5 x 1 1 0 v0 x to v6 x 1 1 1 v0 x to v7 x software mode sequen cer in software mode, the ad7616 - p contains a 32 - layer fully configurable sequencer stack. control of the sequencer is achieved by programming the configuration register and sequencer stack registers via the parallel interface. each stack layer can be individually programmed to pair any input from analog input vxa to any input from analog input vxb , or any diagnostic channel can be selected for conversion. the sequencer depth can be set to any length from 1 to 32 layers . the sequencer depth is controlled via the ssrenx bit. set the ssrenx bit in the sequencer stack register corresponding to the last step required. the channels to convert are selected by programming the aselx and bselx bits in each sequence stack register for the depth required. the sequen cer is activated by setting the seqen bit in the configuration register to 1. figure 54 . hardware mode sequencer configuration reset seqen convst busy ch x ch y ch z chsel0 to chsel2 a/b 0 a/b x ? 1 a/b y ? 1 a/b x a/b 0 a/b y a/b 0 data initial setup configure point configure point 15695-055
data sheet ad7616- p rev. 0 | page 31 of 46 figure 55 . software mode sequencer configura tion to configure and enable the sequencer , it is recommended to complete the following procedure (see figure 55) : 1. configure the analog input range for the required analog input channels . 2. program the sequencer stack registers to select the channels for the sequence . 3. set the ssr en x bit in the last required sequence step . 4. set the seqen bit in the configuration register . 5. provide a dummy convst pulse . 6. cycle through convst pulses and conversion reads to step through each element of the sequencer stack . the sequence automatically restarts from the first element in the sequencer stack with the next convst pulse . following a partial re set, the sequencer pointer is repositioned to the first layer of the stack, but the register programmed values remain unchanged. burst sequencer burst mode avoids generating a convst pulse for each step in a sequence of conversions. one convst pulse conver ts every step in the sequence. the burst sequencer is an additional feature that works in conjunction with the sequencer. if the burst function is enabled, one convst pulse initiates a conversion of all the channels configured in the sequencer. the burst f unction avoids generating a convst pulse for each step in a sequence of conversions , as is the case when the burst function is disabled. configuration of the burst function varies depending on the mode of operation: hardware or software mode. see the hardware mode burst section and the software mode burst section for specific details on configuring the burst function in each mode. when configured, the burst sequence is initiated at the rising edge of convst. the busy pin goes high to indicate that a conversion is in progress. the busy pin remain highs until all conversions in the sequence are complete. the conversion results are available for read back after the busy pin goes low. the number of data reads required to read all the data in the burst sequence is dependent on the length of the sequence configured. the conversion results are presented on the parallel data bus in the same order as the programmed sequence. the t hroughput rate of the ad7616 - p is limited in burst mode and dependent on the length of the sequence. each channel pair requires an acquisition, conversion , and readback time. the time taken to complete a sequence with number of channel pairs, n, is estimated by t burst = ( t conv + 25 ns) + ( n C 1)( t acq + t conv ) + n ( t rb ) w here : t conv is the typical conversion time . t acq is typical acquisition time. t rb is the time required to r ead back the conversion results . hardware mode burst burst mode is enabled in hardware mode by setting the wr / burst pi n to 1. the seqen pin must also be set to 1 to enable the se quencer. in hardware mode, the burst sequencer is controlled by the burst, seqen, and chselx pins. the burst sequencer is enabled or disabled when the ad7616 - p is released from full reset. the logic level of the seqen pin and the burst pin when the reset pin is released determines whether the burst sequencer is enabled or disabled. after the reset pin is released, the burst sequencer function is fixed and a full reset via the reset pin is required to exit the function and set up an alternative configuration. when the burst sequencer is enabled, the logic levels of the chselx pins determine the channels selected for conversion in the burst sequence. the chselx pins at the time reset is released determine the initial settings for the channels to convert in the burst sequence. to reconfigure the channels selected for conver - sion after a reset , set the chselx pins to the required setting for the duration of the next busy pulse (see figure 56 for further details). software mode burst in software mode, the burst function is enabled by setting the burst en bit in the configuration register to 1. this action must be performed when setting the seqen bit in the configuration register as outlined in the steps described in the software mode sequencer section to configure the sequencer (see figure 57 for additional information). reset convst busy register setup a/b 0 s 0 s 1 s n ? 1 s n s 0 data initial setup sequence start dummy conversion sequence start 15695-056
ad7616- p data sheet rev. 0 | page 32 of 46 figure 56 . burst sequencer , hardware mode figure 57 . burst sequencer , software mode reset seqen burst convst busy ch x ch y ch z ch z ch z chsel2 to chsel0 a/b 0 a/b x?1 a/b x a/b 0 a/b y?1 a/b y a/b 0 a/b z?1 a/b z data configure point configure point configure point initial setup 15695-057 reset convst busy register setup a/b 0 s 0 s 1 s n?1 s n s 0 s 1 s n?1 s n data dummy conversion 15695-058
data sheet ad7616- p rev. 0 | page 33 of 46 diagnostics diagnostic channels in addition to the 16 analog inputs, vx a and vx b , the ad7616 - p can also convert th e following diagnostic channels: v cc and the analog a ldo voltage . the diagnostic channels are selected for conversion by programming the channel register (see the channel register section) to the corresponding channel identifier. diagnos - tic channels can also be added to the s equencer stack in software mode , but only provide an accurate reading at throughput rates <250 ksps. see figure 58 for a plot of the deviation from the expected value vs. sampling frequency that can be expected when using the diagnostic channel s. the expected output for each channel is governed by t he following transfer functions: ( ) ( ) ref ref cc cc v v v code v = 5 768 , 32 C 4 ( ) ( ) ( ) ref ref aldo v v v code ldo = 10 768 , 32 7 C 10 figure 58 . deviation from expected value vs. sampling frequency figure 59 . v cc diagnostic transfer function figure 60 . aldo diagnostic transfer function interface self test it is possible to test the integrity of the digital interface by selecting the communication self test channel in the channel register (see the channel register section) . selecting the communication self test for conversion forces the conversion result register to a known fix ed output. when the conversion code is read, c ode 0xaaaa is output as the conversion code of adc a, and c ode 0x5555 is output as the conversion code of adc b. crc the ad7616 - p has a crc checksum mode to improve interface robustness by detecting errors in data . the crc feature is available only in software mode . the crc feature is not available in hardware mode. the crc result is contained within the status register. enabling the crc feature enables the status register and vice versa . the crc function is enabled by setting either the crcen bit or the statusen bit in the configuration register to 1 (see the configuration register s ection). after being enabled, the crc result i s appended to the conversion result and consists of a 16 - bit word, where the first eight bits contain the channel id of the last channel pair converted and the last eight bits are the crc result. the result is accessed via an extra read command, as shown in figure 61. if the crc function is enabled, a crc is calculated on the conversion results for c han nel vx a and c hannel vx b . the crc is calculated and transferred on the parallel interface after the con ve rsion results are transmitted, depending on the configuration of the device. the hamming d istance varies relative to the number of bits in the conversion result. for conversions with 119 bits , the hamming d istance is 4. for >119 bits , the hamming d istance is 1, that is, 1 - bit errors are always detected. 750 ?750 ?500 ?250 0 250 500 0 600 500 400 300 200 100 sampling frequency (ksps) deviation from expected value (codes) aldo error v cc error 15695-059 29000 22000 23000 24500 26000 28000 25000 27000 4.50 4.75 5.00 5.50 5.25 expected output (codes) v cc (v) 15695-060 29000 22000 23000 24500 26000 28000 25000 27000 4.50 4.75 5.00 5.50 5.25 expected output (codes) v cc (v) 15695-060
ad7616- p data sheet rev. 0 | page 34 of 46 the following is a pseudocode description of how the crc is implemented in the ad7616 - p : crc = 8?b0; i = 0; x = number of conversion channel pairs; for (i=0, i data sheet ad7616- p rev. 0 | page 35 of 46 r egister summary the ad7616 - p has six read/write registers for configuring the device in software mode , an additional 32 sequencer stack registers for programming the flexible on - chip sequencer , and a read only status register. table 17 shows an overview of the read/write registers available on the ad7616 - p . the status register is an additional read only register tha t contains information on the channel pair previously converted and the crc result. table 17. regis ter summary 1 reg . name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset r / w 0x02 configuration r egister [15:8] addressing reserved 0x0000 r/w [7:0] sdef bursten seqen os statusen crcen 0x03 channel r egister [15:8] addressing reserved 0x0000 r/w [7:0] chb cha 0x04 input range register a1 [15:8] addressing reserved 0x00ff r/w [7:0] v3 a v2 a v1 a v0 a 0x05 input range register a2 [15:8] addressing reserved 0x00ff r/w [7:0] v7 a v6 a v5 a v4 a 0x06 input range register b1 [15:8] addressing reserved 0x00ff r/w [7:0] v3 b v2 b vb1 v0 b 0x07 input range register b2 [15:8] addressing reserved 0x00ff r/w [7:0] v7 b v6 b vb5 v4 b 0x20 to 0x3f sequencer stack registers[0:31] [15:8] addressing ssren x 0x0000 2 r/w [7:0] bsel x asel x n/a status r egister [15:8] a[3:0] b[3:0] n/a r [7:0] crc[7:0] 1 n/a means not applicable. 2 after a full or partial rest is issued, the sequencer stack register is reinitialized to cycle through channel v0a and channel v0b to channel v7a and channel v7b. the remaining 24 layers of the stack are reinitialized to 0x0.
ad7616- p data sheet rev. 0 | page 36 of 46 addressing register s the seven msbs written to the device are decoded to determine the register that is addressed. the seven msbs consist of the register address (regaddr) , b its[5:0] , and the read/write bit. the register address bits determine the on - chip register that is selected. the read/write bit determines whether the remaining nine bits of data on the db x lines are loaded into the addressed register. if the read/write bit is 1 , the bits load into the reg i ster addressed by the register select bits. if the read/wri te bit is 0 , the command is seen as a read request. the addressed register data is available to be read during the next read operation. msb lsb d15 d14 d13 d12 d11 d10 d9 d8 to d0 w/ r reg addr[5] reg addr[4] reg addr[3] reg addr[2] reg addr[1] regaddr[0] data [8:0] table 18. bit mnemonic description d15 w / r if a 1 is written to this bit , b its[ d 8: d 0] of this register are written to the register specified by regaddr[5:0]. alternatively, if a 0 is written , the next operation is a read from the designated register. d14 regaddr[5] if a 1 is written to this bit, the contents of re gaddr[4:0] specifies the 32 sequencer stack r egisters. alternatively , i f a 0 is written to this bit, a register is selected as defined by regaddr[4:0] . [ d13 : d9 ] regaddr[4:0] when w/ r =1, the contents of regaddr[4:0] determine the re giste r for selection , as follows : 00001 : r eserved . 00010 : s elects the c onfiguration r egister . 00011 : s elects the c hannel r egister . 00100 : s elects input range register a1 . 00101 : s elects input range register a2 . 00110 : s elects input range register b1 . 00111 : s elects input range register b2 . 01000 : s elects the s tatus r egister when w/ r = 0 and regaddr[4:0] contains 00000, the conversion codes are read . [d8: d0 ] data [8:0] these bits are written into the corresponding register specified by regaddr[5:0] . see the following sections for detailed descriptions of each register.
data sheet ad7616- p rev. 0 | page 37 of 46 configuration regist er the configuration register is used in software mode to configure many of the main functions of the adc, including the s equencer, b urst m ode, o versampling , and crc options. address: 0x02, res et: 0x0000, name: configuration register table 19. bit d escriptions for the configuration register bits bit name settings description reset 1 access [15:9 ] addressing 0 bits[15:9] define the address of the relevant register. see the addressing registers section for further details. 0x0 rw 8 reserved reserved . 0x0 r/w 7 sdef self d etect or e rror f lag . n/a r 0 test passed . the ad7616 -p configured itself after power - up. 1 test failed. an issue was detected during device configuration. a reset is required. 6 bursten burst m ode e nable. 0x0 rw 0 burst m ode is disabled. each channel pair to be converted requires a c o nvst pulse. 1 a single c o nvst pulse converts every channel pair programmed in the 32 - layer sequencer stack registers up to and including the layer defined by the ssren x bit. see the software mode sequencer section and the software mode burst section for further details. 5 seqen channel s equencer e nable. 0x0 rw 0 the channel sequencer is disabled. 1 the channel sequencer is enabled. [4:2] os oversampling (os) r atio , samples per channel. 0x0 rw 000 oversampling disabled. 001 oversampling enabled, osr = 2 . 010 oversampling enabled, osr = 4 . 011 oversampling enabled, osr = 8 . 100 oversampling enabled, osr = 16 . 101 oversampling enabled, osr = 32 . 110 oversampling enabled, osr = 64 . 111 oversampling enabled, osr = 128 . 1 statusen status r egister o utput e nable . 0x0 rw 0 the status register is not read out when reading the conversion result . 1 the status register is read out at the end of all the conversion words (including the self test channel if enabled in s equencer mode) i f all the selected channels are read out. the crc result is included in the last eight bits. 0 crcen crc enable. the statusen and crcen bits have identical functionality. 0x0 rw 1 n/a means not applicable. crc enable status register output enable self-detector error flag os ratio samples per channel 111: os128. 110: os64. 101: os32. 100: os16. 011: os8. 010: os4. 001: os2. 000: os1. burst mode enable channel sequencer enable 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 10 0 11 0 12 0 13 0 14 0 15 0 [15:9] addressing (r/w) [0] crcen (r/w ) [8 ] reserved [1] statusen (r/w ) [7] sdef (r) [4:2] os (r/w) [6] bursten (r/w ) [5] seqen (r/w)
ad7616- p data sheet rev. 0 | page 38 of 46 channel register address: 0x0 3, reset: 0x0000, name: channel register in software manual mode, t he c hannel r egister select s the input channel or self test channel for the next conversion. table 20. bit d escriptions for the channel register bits bit name settings description reset access [15:9 ] addressing bit s [ 15:9] define the address of the relevant register. see the addressing registers section for further details. 0x0 r/w 8 reserved reserved . 0x0 r/w [7:4] chb channel selection bits for adc b c hannels. 0000 v0b. 0001 v1b. 0010 v2b. 0011 v3b. 0100 v4b. 0101 v5b. 0110 v6b. 0111 v7b. 1000 v cc . 1001 aldo. 1010 reserved. 1011 0x5555. set the dedicated bits for digital interface communication self test function. when conversion codes are read, code 0x5555 is output as the conversion code of channel b. 1100 reserved. [3:0] cha channel selection bits for adc a channels. settings are the same as for adc b. 0x0 r/w 0000 v0a. 0001 v1a. 0010 v2a. 0011 v3a. 0100 v4a. 0101 v5a. 0110 v6a. 0111 v7a. 1000 v cc . 1001 aldo. 1010 reserved. 1011 0xaaaa. set the dedicated bits for digital interface communication self test function. when conversion codes are read, code 0xaaaa is read out as the conversion code of channel a. 1100 reserved. channel selection bits for adc a channels 1100: reserved. 1011: 0 xaaaa. 1010: reserved. ... 10: v2 a. 1: v1 a. 0: v0 a. channel selection bits for adc b channels 1100: reserved. 1011: 0x5555. 1010: reserved. ... 10: v2 b. 1: v1 b. 0: v0 b. 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 10 0 11 0 12 0 13 0 14 0 15 0 [15:9] addressing (r/w) [3:0] cha (r/w ) [8 ] reserved [7:4] chb (r/w )
data sheet ad7616- p rev. 0 | page 39 of 46 i nput range registers i nput range register a1 and input range register a2 se lect from one of the three possible input ranges (10 v, 5 v , or 2.5 v) for analog input v0 a to analog input v 7 a . i nput range register b1 and input range register b2 select from one of the three possible input ranges (10 v, 5 v , or 2.5 v) for analog input v0 b to analog input v7 b . input range register a1 address 00 reset 000ff ame input range register a1 tale 21 bit d escriptions for inpu t range register a1 bits bit name settings description reset access [15:9 ] addressing bits[15:9] define the address of the relevant register. see the addressing registers section for further details. 0x0 r/w 8 reserved reserved . 0x0 r/w [7:6] v3 a v3 a v oltage r ange s election . 0x3 r/w 0 0 v3a 10 v . 0 1 v3a 2.5 v. 10 v3a 5 v. 11 v3a 10 v . [5:4] v2 a v2 a voltage range selection. 0x3 r/w 0 0 v2a 10 v . 0 1 v2a 2.5 v. 10 v2a 5 v. 11 v2a 10 v . [3:2] v1 a v1 a voltage range selection. 0x3 r/w 00 v1a 10 v. 01 v1a 2.5 v. 10 v1a 5 v. 11 v1a 10 v. [1:0] v0a v0 a voltage range selection. 0x3 r/w 00 v0a 10 v. 01 v0a 2.5 v. 10 v0a 5 v. 11 v0a 10 v. v0a voltage range selection v1a voltage range selection v3a voltage range selection v2a voltage range selection 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 0 9 0 10 0 11 0 12 0 13 0 14 0 15 0 [15:9] addressing (r/w ) [1:0] v0a (r/w) [8 ] reserved [3:2] v1a (r/w) [7:6] v3a (r/w) [5:4] v2a (r/w)
ad7616- p data sheet rev. 0 | page 40 of 46 input range register a2 address: 0x05, reset: 0x00ff, name: input range register a2 table 22. bit d escriptions for input range register a2 bits bit name settings description reset access [15:9 ] addressing bits [15:9] define the address of the relevant register. see the addressing registers section for further details. 0x0 r/w 8 reserved reserved . 0x0 r/w [7:6] v7 a v7a voltage range selection. 0x3 r/w 00 v7a 10 v. 01 v7a 2.5 v. 10 v7a 5 v. 11 v7a 10 v. [5:4] v6 a v6a voltage range selection. 0x3 r/w 00 v6a 10 v. 01 v6a 2.5 v. 10 v6a 5 v. 11 v6a 10 v. [3:2] v5 a v5a voltage range selection. 0x3 r/w 00 v5a 10 v. 01 v5a 2.5 v. 10 v5a 5 v. 11 v5a 10 v. [1:0] v4 a v4a voltage range selection. 0x3 r/w 00 v4a 10 v. 01 v4a 2.5 v. 10 v4a 5 v. 11 v4a 10 v. reserved v4a voltage range selection v5a voltage range selection v7a voltage range selection v6a voltage range selection 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 0 9 0 10 0 11 0 12 0 13 0 14 0 15 0 [15:9] addressing (r/w ) [1:0] v4a (r/w) [8 ] reserved [3:2] v5a (r/w) [7:6] v7a (r/w) [5:4] v6a (r/w)
data sheet ad7616- p rev. 0 | page 41 of 46 input range register b1 address: 0x06, reset: 0x00ff, name: input range register b1 table 23. bit d escriptions for input range register b1 bits bit name settings description reset access [15: 9 ] addressing bits[ 15:9] define the address of the relevant register. see the addressing registers section for further details. 0x0 r/w 8 reserved reserved . 0x0 r/w [7:6] v3 b v3b voltage range selection. 0x3 r/w 00 v3b 10 v. 01 v3b 2.5 v. 10 v3b 5 v. 11 v3b 10 v. [5:4] v2 b v2b voltage range selection. 0x3 r/w 00 v2b 10 v. 01 v2b 2.5 v. 10 v2b 5 v. 11 v2b 10 v. [3:2] v 1 b v1 b voltage range selection. 0x3 r/w 00 v 1 b 10 v. 01 v 1 b 2.5 v. 10 v 1 b 5 v. 11 v 1 b 10 v. [1:0] v0 b v0b voltage range selection. 0x3 r/w 00 v0b 10 v. 01 v0b 2.5 v. 10 v0b 5 v. 11 v0b 10 v. v0b voltage range selection v1b voltage range selection v3b voltage range selection v2b voltage range selection 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 0 9 0 10 0 11 0 12 0 13 0 14 0 15 0 [15:9] addressing (r/w ) [1:0] v0b (r/w) [8 ] reserved [3:2] v1b (r/w) [7:6] v3b (r/w) [5:4] v2b (r/w)
ad7616- p data sheet rev. 0 | page 42 of 46 input range register b2 address: 0x07, reset: 0x00ff, name: input range register b2 table 24. bit d escriptions for input range register b2 bits bit name settings description reset access [15:9 ] addressing bits[ 15:9] define the address of the relevant register. see the addressing registers section for further details. 0x0 r/w 8 reserved reserved . 0x0 r/w [7:6] v7 b v7b voltage range selection. 0x3 r/w 00 v7b 10 v. 01 v7b 2.5 v. 10 v7b 5 v. 11 v7b 10 v. [5:4] v6 b v6b voltage range selection. 0x3 r/w 00 v6b 10 v. 01 v6b 2.5 v. 10 v6b 5 v. 11 v6b 10 v. [3:2] v5 b v5b voltage range selection. 0x3 r/w 00 v5b 10 v. 01 v5b 2.5 v. 10 v5b 5 v. 11 v5b 10 v. [1:0] v4 b v4b voltage range selection. 0x3 r/w 00 v4b 10 v. 01 v4b 2.5 v. 10 v4b 5 v. 11 v4b 10 v. sequencer stack regi s ter s although the channel register define s the next chann el for conversion (be it a diagnostic channel or pair of analog input channels) , to sample numerous analog input channel s , the 32 sequencer stack register s offer a convenient solution. w ithin the communication register , when the regaddr5 bit is set to l ogic 1, the contents of regad dr[4:0] spe cif y 1 of the 32 sequencer stack registers . within each sequencer stack register , the user can define a pair of analog inputs to sample simultaneously. the structure of the sequence forms a stack, in which each row represents two channels to convert simultaneously. the sequenc e begins with s equencer s tack r egister 1 and cycles through to s equencer s tack r egister 32. if b it d8 ( the enable bit , ssren x) with in a sequencer stack register is set to 1, the sequence ends with the pair of analog inputs defined by that register , then returns to the first sequencer stack register , and resumes the cycle again. v4b voltage range selection v5b voltage range selection v7b voltage range selection v6b voltage range selection 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 0 9 0 10 0 11 0 12 0 13 0 14 0 15 0 [15:9] addressing (r/w ) [1:0] v4b (r/w) [8 ] reserved [3:2] v5b (r/w) [7:6] v7b (r/w) [5:4] v6b (r/w)
data sheet ad7616- p rev. 0 | page 43 of 46 by default , the first eight layers of the s equencer sta ck r egisters are programmed to cycle through analog input v0 a and analog input v0 b to analog input v7 a and analog input v7 b . after a full or p artial reset is issued, the s equencer s tack r egister re initialize s to cycle through analog input v0 a and analog input v0 b to analog input v7 a and analog input v7 b . the remaining sequencer stack registers are reinitialized to 0x0000. sequencer stack register 0 to sequencer stack register 7 address: 0x20 to 0x27 , reset: 0x0000, 0x0011, 0x0022, 0x0033, 0x0044, 0x0055, 0x0066, 0x0 0 77, name: sequencer stack register 0 to sequencer stack register 7 table 25. bit d escriptions for sequencer stack register 0 to sequencer stack register 7 bits bit name settings description reset access [15: 9 ] addressing bits [15:9] define the address of the relevant register. see the addressing registers section for further details. 0x0 r/w 8 ssren x setting this bit to 0 instructs t he adc to move to the next layer of the sequencer stack after converting the present channel pair. setting this bit to 1 defines that layer of the sequencer stack as the final layer in the sequence. thereafter, the sequencer loops back to the first layer of the stack. 0x0 r/w [7:4] bsel x channel selection bits for adc b channels. 0x0 1 r/w 0000 v 0 b . 0001 v 1 b . 0010 v 2 b . 0011 v 3 b . 0100 v 4 b . 0101 v 5 b . 0110 v 6 b . 0111 v 7 b . 1000 v cc . 1001 aldo . 1010 reserved . 1011 set the dedicated bits for digital interface communication self test function. when the conversion codes is read, c ode 0xaaaa is read out as the conversion code of c hannel a, and c ode 0x5555 is output as the conversion code of c hannel b. 1100 reserved. [3:0] asel x channel selection bits for adc a channels . settings are the same as for adc b. 0x0 1 r/w 1 by default, the first eight layers of the sequencer stack registers are programmed to cycle through analog inp ut v0a and analog input v0b to analog input v7a and analog input v7b. after a full or partial reset is issued, the sequencer stack register reinitializes to cycle through analog input v0a and analog input v0b to analog input v7a and analog input v7b. the r emaining sequencer stack registers are reinitialized to 0x0000. channel selection bits for adc a channels defines final layer of stack channel selection bits for adc b channels 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 10 0 11 0 12 0 13 0 14 0 15 0 [15:9] addressing (r/w ) [3:0] aselx (r/w) [8] ssrenx (r/w ) [7:4] bselx (r/w)
ad7616- p data sheet rev. 0 | page 44 of 46 sequencer stack register 8 to sequencer stack register 31 address: 0x28 to 0x3f, reset: 0x00, name: sequencer stack register 8 to sequencer stack register 31 table 26 . bit descriptions for sequencer stack register 8 to sequencer stack register 31 bits bit name settings description reset access [15:9] addressing bits[ 15:9] define the address of the relevant register. see the addressing registers section for further details. 0x0 r/w 8 ssrenx setting this bit to 0 instructs the adc to move to the next layer of the sequencer stack after converting the present channel pair. setting this bit to 1 defines that layer of the sequencer stack as the final layer in the sequence. thereafter, the sequencer loops back to the first layer of the stack. 0x0 r/w [7:4] bselx channel selection bits for adc b channels. 0x0 r/w 0000 v0b. 0001 v1b. 0010 v2b. 0011 v3b. 0100 v4b. 0101 v5b. 0110 v6b. 0111 v7b. 1000 v cc . 1001 aldo. 1010 reserved. 1011 set the dedicated bits for digital interface communication self test function. when the conversion codes is read, code 0xaaaa is read out as the conversion code of channel a, and code 0x5555 is output as the conversion code of channel b. 1100 reserved. [3:0] aselx channel selection bits for adc a channels. settings are the same as for adc b. 0x0 1 r/w channel selection bits for adc a channels defines final layer of stack channel selection bits for adc b channels 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 10 0 11 0 12 0 13 0 14 0 15 0 [15:9] addressing (r/w ) [3:0] aselx (r/w) [8] ssrenx (r/w ) [7:4] bselx (r/w)
data sheet ad7616- p rev. 0 | page 45 of 46 status register the status register is a 16 - bit read only register. if the status en bit or the crcen bit is set to l ogic 1 in the configuration register , the status register is read out at the end of all conversion words for the selected channels, including the self test channel if enabled in sequencer mode. see the crc section and figure 61 for more information . msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a[3:0] b[3:0] crc[7:0] table 27. bit d escriptions for status register bit s bit name settings description reset 1 access [ d15 : d12 ] a[3:0] channel i ndex for previous conversion result on c hannel a . n/a r [ d1 1: d8 ] b[3:0] channel i ndex for previous conversion result on c hannel b . n/a r [ d7 : d0 ] crc [7:0] crc calculation for the previous conversion result(s). refer to the crc section for further detail s . n/a r 1 n/a means not applicable.
ad7616- p data sheet rev. 0 | page 46 of 46 outline d imensions figure 62 . 80 - l ead low profile quad flat p ackage [lqfp] (st - 80 - 2) dimensions shown in millimeters ordering guide model 1 junction temperature range package description package option ad7616 - pbstz ? 40c to +12 5c 80 - lead low profile quad flat package [lqfp] st -80 -2 ad7616 - pbstz -rl ? 40c to +12 5c 80 - lead low profile quad flat package [lqfp] st -80 -2 eval - ad7616 - psdz evaluation board 1 z = rohs compliant part. compliant t o jedec s t andards ms-026-bec 1.45 1.40 1.35 0.15 0.05 0.20 0.09 0.10 coplanarit y view a ro ta ted 90 ccw se a ting plane 7 3.5 0 61 60 1 80 20 41 21 40 view a 1.60 max 0.75 0.60 0.45 16.20 16.00 sq 15.80 14.20 14.00 sq 13.80 0.65 bsc lead pitch 0.38 0.32 0.22 t op view (pins down) pin 1 051706- a ? 2017 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owne rs. d15695 - 0- 6/17(0)

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